1. Field of the Invention
The present invention relates to a pipeline type A/D converter apparatus configured by, for example, VLSI, and provided with a precharge circuit.
2. Description of the Related Art
Under present circumstances where analog-digital consolidation system LSIs play great roles in accordance with developments in the communication and video technologies, a reduction in the power consumption of consolidation system LSIs is a matter of major concern. The progresses in the semiconductor fine processing technology have caused increases in the performance and integration of digital circuits and achieved efficient power reductions with lowered power voltages. On the other hand, A/D converters of analog circuits, which have become easily increased in speed by virtue of improvements in the basic performances of transistors, still need to cope with device variations on processes, deteriorations in the signal-to-noise ratio (hereinafter referred to as SNR) due to lowered voltages and so on, and this leads to difficulties in the circuit design for obtaining reliable performances.
In general, high-resolution pipeline type A/D converters need a large sampling capacitance to secure a high SNR, and it is unavoidable to increase the power consumption of an amplifier for charge and discharge of the capacitance. Nevertheless, the pipeline architecture is put to practical use as an A/D converter that can achieve high speed and high resolution with low power consumption as compared with the other conversion systems.
A prior art pipeline type A/D converter apparatus will be described below. The pipeline A/D converter apparatus configured by including a multistage cascade connection of low-resolution A/D converters is the architecture that can achieve high speed and high resolution with a comparatively low power consumption as compared with the A/D converter apparatuses of the other systems, and the architecture serve as the mainstream in the speed range of sampling frequencies of several megahertz to several hundreds of megahertz with a resolution of 8 to 14 bits.
FIG. 3 is a block diagram showing a configuration of a prior art A/D converter circuit part ADa(k). Referring to FIG. 3, the circuit part is constituted of a pre-A/D converter circuit (hereinafter referred to as an ADC circuit) 21a and a multiplication type D/A converter circuit (hereinafter referred to as an MDAC (Multiplying Digital to Analog Converter) circuit) 26 of the so-called basic arithmetic circuit. In this case, the MDAC circuit 26 is constituted of a D/A converter circuit (hereinafter referred to as a DAC circuit) 22a, four switches SW1 to SW4, sampling capacitances C1 and C2 and an operational amplifier A1.
The circuit part is constituted of a pipeline stage of a MDAC circuit 26, which is the basic computing circuit that receives an analog input signal by a sample holding circuit, subsequently doubles the input voltage and performs subtraction and addition of a reference voltage, and a sub-A/D converter circuit 21a of a comparator. Each stage operates in a pipeline manner by alternately repeating a “sampling mode” and an “amplification mode” and delivering operation results every half clock to the subsequent stages from the input to the final stage. The resolution is determined depending on a resolution per stage and the number of stages of the pipeline.
A high-resolution pipeline A/D converter apparatus needs large signal amplitude for securing the SNR (Signal to Noise Ratio) and large sampling capacitances C1 and C2 for suppressing thermal noises generated from the operational amplifier A1 and switches SW1 to SW4. The power consumption of the pipeline A/D converter apparatus is dominated by a bias current of the operational amplifier A1 used in the sample holding circuit of the input part and the following pipeline stages. In order to perform sampling at high speed for a large capacitance value, it is necessary to increase the bias current to perform quick charge and discharge, and an increase in the power consumption is a concern.
FIG. 4 is a block diagram showing operations of prior art A/D converter circuit parts ADa(i) and ADa(i+1). FIG. 4 shows an operation of general 1.5 bits/stage pipeline A/D converter circuit parts ADa(i) and ADa(i+1). When the i-th stage is set in the sampling mode, the two sampling capacitances C1 and C2 sample an input voltage Vin. Subsequently, in the amplification mode, the bottom electrode of the sampling capacitance C1 is connected to the reference voltage of the D/A converter, and the bottom electrode of the sampling capacitance C2 is connected to an output voltage terminal (Vout) according to the judgment result of the ADC circuit 21a of the comparator. An output voltage at this time is transferred to the next stage that is set in the sampling mode. In the redundant binary 1.5 bits/stage system, the output signal from the ADC circuit 21a of the comparator is encoded into a digital value of Diε{−1, 0, 1}, and the input to output characteristics of the pipeline stage can be expressed by the following Equations:
                                                        Vout              =                            ⁢                                                2                  ⁢                  Vin                                -                Vr                                                                                      ⁢                                                                    for                    ⁢                                                                                  ⁢                    Di                                    =                  1                                ;                                                                                        =                            ⁢                              2                ⁢                Vin                                                                                      ⁢                                                                    for                    ⁢                                                                                  ⁢                    Di                                    =                  0                                ;                                                                                        =                            ⁢                                                2                  ⁢                  Vin                                +                Vr                                                                                      ⁢                                                                    for                    ⁢                                                                                  ⁢                    Di                                    =                                      -                    1                                                  ,                                                                        (        1        )            
where Vin denotes an input signal voltage of the pipeline stage, Vout denotes an output signal voltage of the pipeline stage, and Vr denotes a reference voltage of A/D conversion. In terms of the circuit structure, the sampling capacitances C1 and C2 of the next stage need to be charged to a predetermined value with the output voltage of the operational amplifier A1 at the moment of phase switchover from the “sampling mode” to the “amplification mode”. Since the inputted signal is subjected to sequential operation at the pipeline stage, the charging time changes depending on the initial charge charged in the sampling capacitances C1 and C2 of the next stage, and this influences on the settling response. In particular, when the Nyquist frequency that is half the frequency of the sampling frequency becomes an input frequency, the settling becomes slowest due to the influence of charges directly opposite to the voltage to be sampled stored in the next capacitance. The maximum settling time limits the sampling rate of the A/D converter apparatus.
The prior art documents related to the present invention are as follows:
(a) Patent document 1: Japanese patent laid-open publication No. 2003-158434;
(b) Non-patent document 1: K. Iizuka et al., “A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s”, IEEE J. Solid-State Circuits, Vol. 41, pp. 883-890, April 2006;
(c) Non-patent document 2: B. Murman et al., “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplifier”, IEEE Journal on Solid-State Circuits, Vol. 38, pp. 2040-2050, December 2003;
(d) Non-patent document 3: S. Kawahito et al., “Low-Power Design of High-Speed A/D Converters”, IEICE Transactions on Electronics, Vol. E88-C, No. 4, pp. 468-478, April 2005;
(e) Non-patent document 4: D. Kelly et al., “A 3V 340 mW 14 b 75MSPS CMOS ADC with 85SFDR at Nyquist”, ISSCC Digest of Technical Papers, pp. 134-135, February 2001;
(f) Non-patent document 5: H. C. Liu et al., “A 15 b 20 MS/s CMOS Pipelined ADC with Digital Background Calibration”, ISSCC Digest of Technical Papers, pp. 374-375, February 2004;
(g) Non-patent document 6: H. Matsui et al., “A 14-bit digitally self-calibrated pipelined ADC with Adaptive Bias Optimization for Arbitrary Speeds up to 40 MS/s”, IEEE Symposium on VLSI Circuits, pp. 330-333, June 2005; and
(h) Non-patent document 7: P. Bogner et al., “A 14 b 100 MS/s Digitally Self-Calibrated Pipelined ADC in 0.13 μm CMOS”, ISSCC Digest of Technical Papers, pp. 224-225, February 2006.
A method for further reducing the power consumption of the high-resolution pipeline A/D converter is reported on the research level, whereas there is very few reports that has achieved a sufficient performance at high speed and with low power consumption (See, for example, Non-Patent Documents 1 and 2).
The pipeline type A/D converter of the first prior art configured by the multistage cascade connection of low-resolution A/D converters is known as an architecture that can achieve high speed and high resolution with a lower power consumption than that of the other A/D converters (See, for example, Patent Document 1). In the pipeline type A/D converter, the resolution is determined by the resolution per stage and the number of pipeline stages, and the stages alternately repeat the “sampling mode” and the “amplification mode”. A high-resolution pipeline A/D converter needs large signal amplitude for obtaining a high SNR and a large sampling capacitance for suppressing thermal noises generated from the amplifier and the switches. The power consumption of the A/D converter is determined by the sample holding (S/H) circuit of the input part and the bias current of the operational amplifier used at the pipeline stage following the circuit. In order to sample a large capacitance value at higher speed, it is necessary to increase the bias current to quickly perform charge and discharge, and an increase in the power consumption becomes a concern.
Moreover, sharing of an amplifier (amplifier sharing) can be enumerated as one method for power reduction. In the pipeline A/D converter, the amplifier is used only half time with respect to the clock frequency. The sharing is intended to reduce the power consumption by preparing another set of sampling capacitances at the pipeline stage and efficiently using the amplifier by switchover of switches. The amplifier sharing with the interleave configuration (lateral 2-channel system) of the second prior art, in which the other capacitance set enters the amplification mode while one capacitance set performs sampling in a certain pipeline stage, is able to approximately halve the operation frequency of the amplifier itself without changing the overall operation frequency. If the operation frequency of the amplifier becomes slow, the power consumption can easily be reduced since the bias current is allowed to be small (See, for example, Non-Patent Document 3 in which a lateral amplifier sharing type interleave system pipeline type A/D converter is disclosed).
The pipeline A/D converter of the first prior art adopts a method of scaling the sampling capacitance employed at the pipeline stage for lower power consumption. This is intended to reduce power supply to the subsequent stages by reducing in steps the sampling capacitance of the factor related to the accuracy and noises since the pipeline A/D converters suffer less influence of noises and less influence on the speed as they are located in hind stages. However, since the capacitance scaling is the technique generally put into practice, a more effective reduction is demanded.
Moreover, the pipeline type A/D converter of the second prior art needs a reset interval for erasing the sample history that might influence the settling response in the input of the amplifier and for common-mode feedback of the amplifier, and it is difficult to actually reduce the power by half.